System and method for read-while-write with nand memory device

ABSTRACT

System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner.

RELATED APPLICATION DATA

This application is a continuation of U.S. application Ser. No.12/728,472 filed on Mar. 22, 2010, which claims the priority of U.S.Provisional Application No. 61/299,065, filed on Jan. 28, 2010, each ofwhich is hereby incorporated in its entirety by reference.

TECHNICAL FIELD OF THE INVENTION

The technology of the present disclosure relates generally tonon-volatile memory devices, particularly flash memory devices withNAND-type architecture and more particularly to a system and method forperforming simultaneous read operations and write operations in aNAND-type memory device.

BACKGROUND

A flash memory device, such as those used in electronic devices (e.g., adesktop computer, a handheld computer, a mobile telephone, a digitalcamera or any other kind of computer/microcontroller based terminal thatcan use non-volatile memory as a storage medium) may have multiplepartitions. During write operations, data cannot be read from the memoryuntil the write operation is completed. This causes read latency thatmight not be desirable or acceptable for time critical use cases, likedemand paging, for example. In any application, overall systemperformance will be faster if data can be read from read-only partitionswhile write operations are in process.

One example of an application where read latency is critical is thepaging-on-demand-technique, where pages of data are not copied from datastorage to RAM until they are needed. Memory is organized in so-calledblocks and pages, with one page typically consisting of 1 kB or 4 kB inthe demand paging context. A block combines several pages and usuallyhas a size of 16 kB. To reduce the required memory size, only pages thatare currently needed for an application are loaded. Therefore, demandpaging requires simultaneous read and write processes. In NAND flashmemory systems, paging-on-demand may be applied, but a major drawback ofsystems for this technique is that read and write operations cannot beperformed simultaneously.

One proposal by the JEDEC Solid State Technology Association to handlethe situation when there is an ongoing write operation and another writeoperation is requested with an embedded memory (eMMC) is to wait untilthe write operation has been concluded before permitting a readoperation to be requested. Another proposal is to allow interrupting anongoing write operation and thereby shorten the latency for the highpriority read. There are a variety of problems with these approaches.For example, consider a write operation that has been requested to writethe (10) blocks into the eMMC. After writing down four (4) blocks, theoperation or process is interrupted by a high priority read operation orprocess. When the high priority read operation has been concluded, thefile system resumes the write operation in order to write down theremaining six (6) blocks, but then a new high priority read request mayarrive, and the write operation is interrupted again. One of the sourcesof high priority read is demand paging, which is a code executionmethod. During startup of the electronic device or when launching a newapplication, there can be a whole series of page faults that willrequest high priority read operations. In the foregoing scenario, theremay be several seconds delay before the write command can be concluded.

Any of the described features and problems are present in both memorycards and embedded mass storage devices based on flash memory.Therefore, a need exists to provide a method of controlling readprocesses on NAND flash memory cards and embedded mass storage devicesin order to decrease read latency times.

SUMMARY

According to an aspect of the invention, a method, device and computerprogram is disclosed that supports a simultaneous read and writeoperation interface in a NAND memory device by defining a partition thatis configured only to be used for reading content (e.g., high priorityread content). In general, one or more partitions are assigned for highpriority read content (e.g., reading programming code, etc.). One ormore of the remaining partitions are then intended to support bothwriting and non-prioritized reading. The controller portion of thememory device splits one common queue into at least two queues, with thefirst queue configured for reading from the read only partition and thesecond queue for reading and writing partition(s). The two queues areexecuted in parallel. When a write operation has been requested into theread only partition, a temporary write will be made, which is maintainedby the memory controller, into a partition that has read and writecapabilities. Then during system idle time, the temporary writtencontent will be transferred, as a background operation, into the readonly partition.

One aspect of the invention relates to a method for simultaneous readand write operations to be performed in a NAND-type memory device, themethod includes: assigning a first partition in a NAND-type memorydevice, wherein the first partition is configured to perform readoperations on high priority read content; assigning a second partitionin the NAND-type memory device, wherein the second partition isconfigured to perform read operations and write operations, wherein theread operations are performed on non-high priority read content; andcontrolling the first partition and second partition to operate in asimultaneous manner.

Another aspect of the invention relates to the step of controllingincludes forming a first queue and a second queue from a primary queue,wherein the first queue executes read operations associated with thefirst partition and the second queue executes read and write operationsassociated with the second partition.

Another aspect of the invention relates to the first queue and thesecond queue being executed in parallel.

Another aspect of the invention relates to when additional content isrequired to be written to the first partition, a temporary write is madeto the second partition to store the additional content.

Another aspect of the invention relates to when an associated hostdevice requests writing additional content to the first partition, atemporary write is made to the second partition to store the additionalcontent.

Another aspect of the invention relates to transferring the additionalcontent to the first partition during an idle time associated with asystem in which the NAND-type memory device is coupled.

Another aspect of the invention relates to assigning one or moreadditional partitions, wherein at least one of the additional partitionsis configured to perform read operations and write operations.

Another aspect of the invention relates to when the read and/or writeoperations performed by the one or more additional partitions areperformed on non-high priority read content.

Another aspect of the invention relates to controlling the firstpartition, the second partition and the one or more additionalpartitions in parallel.

Another aspect of the invention relates to the step of controllingincluding forming a first queue and a second queue and additional queuesfor each of the additional partitions from a primary queue, wherein thefirst queue executes read operations associated with the first partitionand the second queue executes read operations and write operationsassociated with the second partition and each of the additional queuesexecute read operations and write operations associated with each of theone or more additional partitions.

Another aspect of the invention relates to a non-volatile memory deviceincluding: a NAND-type memory chip including a first partitionconfigured to perform read operations on high priority read content anda second partition configured to perform read operations and writeoperations, wherein the read operations are performed on non-highpriority read content; and a memory controller configured to control thefirst partition and second partition to operate in a simultaneousmanner, such that the first partition may read high priority contentwhen the second partition is reading or writing content.

Another aspect of the invention relates to the memory controllerincluding a first queue for executing read operations associated withthe first partition and a second queue for executing read and writeoperations associated with the second partition

Another aspect of the invention relates to the first queue and thesecond queue being configured to be executed in parallel.

Another aspect of the invention relates to when additional content isrequired to be written to the first partition, the memory controller isconfigured to permit a temporary write to be made to the secondpartition to store the additional content.

Another aspect of the invention relates to when an associated hostdevice requests writing additional content to the first partition, atemporary write is made to the second partition to store the additionalcontent.

Another aspect of the invention relates to the memory controllertransferring the additional content to the first partition during anidle time associated with a host device in which the NAND-type memorydevice is coupled.

Another aspect of the invention relates to including one or moreadditional partitions in the NAND-type memory device, wherein at leastone of the additional partitions is configured to perform readoperations and write operations.

Another aspect of the invention relates to the memory controller beingconfigured for controlling the first partition, the second partition andthe one or more additional partitions in parallel.

Another aspect of the invention relates to the memory controllerincluding a first queue for controlling execution of the firstpartition, a second queue for controlling execution of the secondpartition and additional queues for each additional partition containedon the NAND-type memory chip.

Another aspect of the invention relates to a program for use in anelectronic host device for controlling for simultaneous read and writeoperations to be performed in a NAND-type memory device, wherein theNAND-type memory includes a first partition and a second partition; anda memory controller configured to control the first partition and thesecond partition to execute in a simultaneous manner, wherein the firstpartition is a read only partition dedicated to high priority readcontent and second partition is a read and write partition, the programincluding executable logic to: place high priority read content on thefirst partition; receiving a request for writing additional content onthe first partition; writing the additional content to the secondpartition; and transferring the additional content to the firstpartition when a signal is received from the host electronic device tothe memory control indicating that the host electronic device is in anidle state.

These and further features will be apparent with reference to thefollowing description and attached drawings. In the description anddrawings, particular embodiments of the invention have been disclosed indetail as being indicative of some of the ways in which the principlesof the invention may be employed, but it is understood that theinvention is not limited correspondingly in scope. Rather, the inventionincludes all changes, modifications and equivalents coming within thescope of the claims appended hereto.

Features that are described and/or illustrated with respect to oneembodiment may be used in the same way or in a similar way in one ormore other embodiments and/or in combination with or instead of thefeatures of the other embodiments. It should be emphasized that the term“comprises/comprising” when used in this specification is taken tospecify the presence of stated features, integers, steps or componentsbut does not preclude the presence or addition of one or more otherfeatures, integers, steps, components or groups thereof.

Many aspects of the invention can be better understood with reference tothe following drawings. The components in the drawings are notnecessarily to scale, emphasis instead being placed upon clearlyillustrating the principles of the present invention. To facilitateillustrating and describing some parts of the invention, correspondingportions of the drawings may be exaggerated in size, e.g., made largerin relation to other parts than in an exemplary device actually madeaccording to the invention. Elements and features depicted in onedrawing or embodiment of the invention may be combined with elements andfeatures depicted in one or more additional drawings or embodiments.Moreover, in the drawings, like reference numerals designatecorresponding parts throughout the several views and may be used todesignate like or similar parts in more than one embodiment.

In the present application, embodiments of the invention are describedin the context of an electronic device. It will be appreciated that theinvention is intended to be interpreted broadly to include to any typeof appropriate electronic device, examples of which include a mediaplayer, a gaming device, a PDA, a computer, digital cameras, mobiletelephones, laptops, tablets, other mobile devices capable of showingimages or running computer applications, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exemplary embodiment of a system in accordance with aspectsof the present invention.

FIG. 2 is a flow chart or logic diagram of an exemplary method carryingout the method of the invention and of exemplary functions of theapparatus and program in accordance with aspects of the presentinvention.

FIG. 3 is a flow chart or logic diagram of an exemplary method carryingout the method of the invention and of exemplary functions of theapparatus and program in accordance with aspects of the presentinvention.

FIG. 4 is a flow chart or logic diagram of an exemplary method carryingout the method of the invention and of exemplary functions of theapparatus and program in accordance with aspects of the presentinvention.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments will now be described with reference to the drawings,wherein like reference numerals are used to refer to like elementsthroughout. It will be understood that the figures are not necessarilyto scale.

The invention will be described in connection with a generic hostdevice. It will be appreciated that aspects of the disclosed method maybe applied to electronic devices such as, but not limited to, desktopcomputers, handheld computers, tablet computers, mobile telephones,digital cameras, personal digital assistants, music players, and anyother kind of computer/microcontroller based device that can usenon-volatile memory as a storage medium.

The present invention is described below with respect to a host devicethat includes a NAND-type memory device for simultaneous performance ofread and write operations. In general terms, the NAND-type memory deviceassigns a first partition that is configured to be used exclusively forreading high priority content (e.g., program code, etc). One or morepartitions may be assigned for high priority read content. The remainingpartition or partitions are then intended to support both writeoperation and non-prioritized read operations. The controller portion ofthe memory device will split one common queue into two queues, with thefirst queue for reading from the read only partition and the secondqueue for controlling the other partitions (e.g., partitions configuredto perform read operations and write operations). The two queues areexecuted in parallel. When a request is made to write to the firstpartition (e.g., read only partition) then a temporary write operationwill be made, which places the content into a second partition (e.g., apartition that allows read operations and write operations). Then duringsystem idle time, the temporary written content will be transferred, asa background operation, into the read only partition.

Referring initially to FIG. 1, a system 10 in the form of a host 12 anda memory device 14 is illustrated. The host 12 and the memory device 14may communicate through an interface 16. The external host device 12 maybe represented by a terminal comprising a processor for executingprogram code stored in a storage medium. The host 12 may needinformation stored on the memory device 14 to execute program code or todisplay the information on the host 12, such as an internal flash memoryor a flash memory card in an electronic device. The host 12 may becapable of controlling this memory access and to communicate data withthe memory device 14. For this purpose, the host 12 is connected to thememory controller of the memory device 14. Such communications betweenthe host 12 and the memory device occur over the interface 16. As statedabove, the host 12 may for example be a desktop computer, a handheldcomputer, a mobile telephone, a digital camera or any other kind ofcomputer/microcontroller based terminal that can use non-volatile memoryas a storage medium.

The memory device 14 is a non-volatile memory device and may beprovided, e.g., as a removable memory element (memory card) or asembedded mass storage arranged within the device. The non-volatilememory device 14 comprises at least one NAND type flash memory chip thatincludes a memory controller 20 and a storage element 22. The memorydevice 14 includes a port 24 for facilitating communication between withhost device 12 and the memory device 14 through the interface 16.

The memory control 20 includes a primary queue 26. A queue is aparticular kind of collection in which the entities in the collection(e.g., read/write operations to be performed by the memory device 14)are kept in order and the principal operations on the collection are theaddition of entities to the end position and removal of entities fromthe front terminal position.

The primary queue 26 may have a plurality of queues (e.g., queues 28A,28B, . . . , 28N) formed within the primary queue 18. For example, asshown in FIG. 1, the queues 28A, 28B, . . . , 28N may be formed in theprimary queue 26, where N may be dependent on the number of partitions(30A, 30B, . . . , 30C) formed in the storage element 22, for example.Each of the queues (28A, 28B, . . . , 28N) may be assigned to operate ona certain partition of the in the storage element 22. One of ordinaryskill in the art will readily appreciate that the number of queues maybe independent of the number partitions of storage element 22. Forexample, there may be fewer queues formed in the primary queue 26 thanthere are partitions in the storage element 22. The queues 28A, 28B, . .. , 28N are designed to operate in parallel. That is, the queues 28A,28B, . . . , 28N may simultaneously perform a task stored in eachrespective queue.

One of the queues (e.g., 28A) may be dedicated to performing highpriority read operations in a partition (e.g., 30A) that is dedicated toperforming high priority read operations, for example. There may be morequeues (e.g., 28B) that are also assigned to perform high priority readoperations.

The storage element 22 includes a plurality of partitions (e.g.,partitions 30A, 30B, . . . , 30N). At least one partition (e.g.,partition 30A) is assigned in the memory device 14 and configured toperform read operations on high priority read content. There may beadditional partitions that may be also assigned to perform readoperations on high priority content. For purposes of this disclosure, wewill assume that partition 30A has been assigned and configured to onlyperform read operations on high priority read content.

High priority read content may be determined in a variety of manners.For example, a file containing an application may be assigned to operateon a particular partition. When access to a file has been requested, thememory controller 20 automatically assigns the application to the highpriority read partition and/or corresponding queue. Alternatively or inaddition, a file may have a flag that indicates that the file is a highpriority read content, for example.

The storage element 22 also includes at least one partition (e.g.,partition 30B) that is assigned and configured to perform read and writeoperations on non-high priority read content.

The host 12 may communicate with the memory controller 20 via a hostinterface 16, such that control of the read and write operations mayoptionally be performed by the host 12. Data to be written onto thememory device 14 or to be read from the memory device 14 is alsotransferred via the host interface. The memory controller 20 includesone or more read/write ports 32 of the memory controller 14 that may beused for accessing the partitions (e.g., P₁, P₂, . . . , P_(N)). Forexample, there may be one port 32 or there may be multiple ports forcontrolling whether certain partitions perform read and/or writeoperations on the memory chip 14 according to predefined specifications.As stated above, the storage element 22 includes partitions (e.g., P₁,P₂, . . . , P_(N)), where at least one of the partitions (e.g., P₁) isdedicated to performing read operations on high priority read content(e.g., program code). One or more of the other partitions (e.g., P₂, . .. , P_(N)) may perform read/write operations.

The memory controller 20 is configured allow read access to onepartition (e.g., P₁) while reading or writing to a second partition(e.g., P₂) of the memory device 14. For example, when high priority readcontent is being read by the first partition (P₁) and additional content(e.g., high priority read content) is required to be written to thefirst partition (P₁), a temporary write may be made to a partition thatmay perform read/write operations (e.g., P₂, . . . , P_(N)).

The memory controller 20 prevents overlapping of memory access (e.g.,prevents more than one request being directed to a single partition). Toprevent such overlapping, the memory controller 20 should be aware ofongoing operations anywhere on the memory device 14. When there is anongoing operation or several requests received by the memory controller20, the controller will issue commands in such a way that it is ensuredthat only one command at a time is directed to one partition, forexample

When simultaneous read/write operations are supported by a NAND chip,the memory card controller may issue commands to different partitions ofthe memory device 14. The memory controller 20 is configured tosimultaneously control operations (e.g., act in parallel) on multiplequeues (e.g., 28A, 28B, . . . , 28N) and multiple partitions (e.g., P₁,P₂, . . . , P_(N)). The step of controlling includes forming a firstqueue and a second queue from a primary queue, wherein the first queueexecutes read operations associated with the first partition and thesecond queue executes read and write operations associated with thesecond partition. For example, the first queue (e.g., Q₁) may controlread operations associated with the partition dedicated to performinghigh-priority read content (e.g., P₁) and the second queue (e.g., Q₂)may control read and write operations associated with other partitions.

Turning to FIG. 2, a method 100 for carrying out the invention from thehost perspective 12 will be discussed below with reference to the logicdiagram or flow chart shown therein. The several blocks illustrated inFIG. 2 will be referred to as blocks, steps or functions, whichdepending on context mean the same.

At block 102, an application (e.g., Application X) on the host device 12requests a write operation for non-high priority content. At block 104,the write request is placed into a queue administered by the memorycontroller 20.

At block 106, another application (e.g., Application Y) on the hostdevice 12 requests a read operation for non-high priority read content.At block 108, the read request is placed into the queue administered bythe memory controller 20.

At block 110, another application (e.g., Application Z) on the hostdevice 12 requests reading from a file on the read only partition. Atblock 112, the high priority read request is placed in the queueadministered by the memory controller 20.

At block 114, another application (e.g., Application XY) requestswriting of content into the read only partition. At block 116, the writerequest is placed in the queue administered by the memory controller 20.

Referring to FIG. 3, the logic diagram of a computer program flow chart200 from the memory controller perspective is illustrated as an exampleof a method for carrying out the invention and the operationalinteraction and characterization of the parts and functions of theinvention. The several blocks illustrated in FIG. 3 will be referred toas blocks, steps or functions, which depending on context mean the same.

At block 202, the memory device 12 reads a queue from the memory device14. At block 204, a determination is made if a high priority read isrequested or a non-high priority read is requested. As one of ordinaryskill will appreciate there are a variety of ways to determine whether afile requests a high priority read. For example, an application file maybe configured to be placed on a particular partition (e.g., a partitiondedicated to high-priority read content); the application may alsoinclude a flag or other identifier in the file or attached to the fileto signify that the application file contains high-priority readcontent).

If the queue contains high-priority read content, program flow moves toblock 206. At block 206, the high-priority read content is placed in thequeue for reading high priority content (e.g., Q₁). At block 208, adetermination is made if there is additional high-priority content inthe queue (e.g., Q′) to read. If there is no additional high-prioritycontent to read, program flow loops back to block 208 until the queuecontains high-priority content. If there is additional high-prioritycontent to read, program flow moves to block 210, where a high priorityread operation is executed. Program flow then continues to block 208 todetermine if there is high-priority content remaining in the queue to beread.

If the determination made in block 204 is that the queue does notcontain high priority read content, program flow moves to block 212. Atblock 212, a determination is made if the queue contains a command towrite into the high priority partition (e.g. P₁). If the determinationat block 212 is “yes” (e.g., the queue contains a command to write intothe high priority partition), program flow moves to block 214. At block214, a priority write flag is set. The priority write flag indicatesthere is additional content to write into the first partition.

From block 214 and a negative response determined at block 212, programflow moves to block 216. At block 216, the additional content is placedin the queue for the second partition. At block 218, a determination ismade if there is anything (e.g., a command) in the queue to read. Ifthere is nothing in the queue, program flow loops back to block 218until there is a new command in the queue. If there is a new command toread in the queue, program flow moves to block 220, where execution ofthe requested command is performed. Program flow then continues to block222.

At block 222, a determination is made if the high priority flag has beenset for the current command. If the determination is negative, programflow moves to block 224. At block 224, normal operation of thenon-priority partition is provided. If the determination from block 222is affirmative, program flow moves to block 226. At block 226, thecontent is written into a buffer for high priority read. Program flowmoves to block 228. At block 228, a “MOVE” (or similar) command isstored in a background operation queue in the memory controller. Thebackground operation queue is a queue in the memory controller that isdedicated to background operations.

FIG. 4 is another exemplary method 300 in accordance with aspects of thepresent invention. Method 300 generally operates in parallel to theexemplary method 200 discussed above. At block 302, a determination ismade as to whether the host device 12 has sent a system idle indicationto the memory device 14. If the determination at block 302 is “no”,program flow continues back to block 302 and waits until a system idleindication is received from the host. If the host device 12 has sent asystem idle indication to the memory device 14, the determination atblock 302 is “yes”, which means that the host is idle. Program flow thenmoves to block 304. At block 304, background operations are initiated.At block 306, the queue containing the moving commands associated withthe additional high priority read content stored in a read and writepartition is read. At block 308, a determination is made if the queuecontains any information. If the queue is empty, program flow moves toback block 302 to continue monitoring whether the host device 12 isidle, as discussed above. If the queue is non-empty, the additionalcontent, which was stored temporarily in a read and write partition(e.g., second partition) is transferred into the first partition, asindicated in block 310. At block 312, the additional content is removedfrom the partition in which it was temporarily stored. Program flowproceeds to block 308 and progresses as discussed above.

It will be apparent to a person having ordinary skill in the art ofcomputer programming, and specifically in application programming forelectronic devices using NAND-type memory devices, how to program thehost device 12 to operate and carry out usual logical functionsassociated with the electronic device and the functions and operationdescribed above with respect to the logic diagrams. Accordingly, detailsas to specific programming code have been left out for the sake ofbrevity. Also, while the functions and may be executed by respectiveprocessing devices in accordance with an embodiment, such functionalitycould also be carried out via dedicated hardware or firmware, or somecombination of hardware, firmware and/or software.

Although certain embodiments have been shown and described, it isunderstood that equivalents and modifications falling within the scopeof the appended claims will occur to others who are skilled in the artupon the reading and understanding of this specification.

What is claimed is:
 1. A method for simultaneous read and writeoperations to be performed in a NAND-type memory device, the methodcomprising: assigning a first partition in a NAND-type memory device,wherein the first partition is configured to perform read operations onhigh priority read content; assigning a second partition in theNAND-type memory device, wherein the second partition is configured toperform read operations and write operations, wherein the readoperations are performed on non-high priority read content; andcontrolling the first partition and second partition to operate in asimultaneous manner.
 2. The method of claim 1, wherein the step ofcontrolling includes forming a first queue and a second queue from aprimary queue, wherein the first queue executes read operationsassociated with the first partition and the second queue executes readand write operations associated with the second partition.
 3. The methodof claim 2, wherein the first queue and the second queue are executed inparallel.
 4. The method of claim 3, wherein when additional content isrequired to be written to the first partition, a temporary write is madeto the second partition to store the additional content.
 5. The methodof claim 3, wherein when an associated host device requests writingadditional content to the first partition, a temporary write is made tothe second partition to store the additional content.
 6. The method ofclaim 4 further comprising transferring the additional content to thefirst partition during an idle time associated with a system in whichthe NAND-type memory device is coupled.
 7. The method of claim 1 furtherincluding assigning one or more additional partitions, wherein at leastone of the additional partitions is configured to perform readoperations and write operations.
 8. The method of claim 7, wherein theread and/or write operations performed by the one or more additionalpartitions are performed on non-high priority read content.
 9. Themethod of claim 7 further including controlling the first partition, thesecond partition and the one or more additional partitions in parallel.10. The method of claim 9, wherein the step of controlling includesforming a first queue and a second queue and additional queues for eachof the additional partitions from a primary queue, wherein the firstqueue executes read operations associated with the first partition andthe second queue executes read operations and write operationsassociated with the second partition and each of the additional queuesexecute read operations and write operations associated with each of theone or more additional partitions.
 11. A non-volatile memory devicecomprising: a NAND-type memory chip including a first partitionconfigured to perform read operations on high priority read content anda second partition configured to perform read operations and writeoperations, wherein the read operations are performed on non-highpriority read content; and a memory controller configured to control thefirst partition and second partition to operate in a simultaneousmanner, such that the first partition may read high priority contentwhen the second partition is reading or writing content.
 12. Thenon-volatile memory device of claim 11, wherein the memory controllerincludes a first queue for executing read operations associated with thefirst partition and a second queue for executing read and writeoperations associated with the second partition
 13. The non-volatilememory device of claim 12, wherein the first queue and the second queueare configure to be executed in parallel.
 14. The non-volatile memorydevice of claim 13, wherein when additional content is required to bewritten to the first partition, the memory controller is configuredpermits a temporary write to be made to the second partition to storethe additional content.
 15. The non-volatile memory device of claim 13,wherein when an associated host device requests writing additionalcontent to the first partition, a temporary write is made to the secondpartition to store the additional content.
 16. The non-volatile memorydevice of claim 15, wherein the memory controller transfers theadditional content to the first partition during an idle time associatedwith a host device in which the NAND-type memory device is coupled. 17.The non-volatile memory device of claim 11 further including one or moreadditional partitions in the NAND-type memory device, wherein at leastone of the additional partitions is configured to perform readoperations and write operations.
 18. The non-volatile memory device ofclaim 17, wherein the memory controller is configured for controllingthe first partition, the second partition and the one or more additionalpartitions in parallel.
 19. The non-volatile memory device of claim 18,wherein the memory controller includes a first queue for controllingexecution of the first partition, a second queue for controllingexecution of the second partition and additional queues for eachadditional partition contained on the NAND-type memory chip.
 20. Aprogram for use in an electronic host device for controlling forsimultaneous read and write operations to be performed in a NAND-typememory device, wherein the NAND-type memory includes a first partitionand a second partition; and a memory controller configured to controlthe first partition and the second partition to execute in asimultaneous manner, wherein the first partition is a read onlypartition dedicated to high priority read content and second partitionis a read and write partition, the program comprising executable logicto: place high priority read content on the first partition; receiving arequest for writing additional content on the first partition; writingthe additional content to the second partition; and transferring theadditional content to the first partition when a signal is received fromthe host electronic device to the memory control indicating that thehost electronic device is in an idle state.